1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having an integrated circuit which includes transistors formed over an insulating surface. In particular, the invention relates to a manufacturing method of a semiconductor device using a high-resolution lithography technique.
2. Description of the Related Art
As a semiconductor device which performs transmission/reception of instructions or data with radio signals, a semiconductor device which includes an integrated circuit having thin film transistors (hereinafter also referred to as “TFTs”) formed over a glass substrate as well as an antenna attached thereto is known (for example, see Reference 1: Japanese Published Patent Application No. 2005-202947).
Such a semiconductor device is called an IC card or an IC tag depending on the use or modes, and is planned to be used for identification of goods or individuals. That is, it has been attempted to introduce identification systems with higher data recording density into commercial transactions or safety control, replacing barcode systems that are widely used presently.
By the way, a conventional manufacturing process of a conventional semiconductor device requires a lithography process (i.e., photolithography process) for forming micropatterns such as wirings or contact holes. The lithography process includes the steps of (1) depositing a photoresist film over a substrate, (2) exposing the photoresist film to light through a mask having predetermined patterns, and (3) developing the photoresist film with a developer, thereby forming desired patterns of an integrated circuit.
FIGS. 18A to 18D illustrate a conventional lithography process. FIG. 18A is a cross-sectional view of a photomask 902 in which a light-shielding film 904 made of chrome or the like is formed on a light-transmissive substrate. Light that has traveled through an opening 903a of the photomask 902 has the same phase and amplitude distribution as light that has traveled through an opening 903b of the photomask 902, as shown in FIG. 18B. FIG. 18C shows light intensity distribution on the exposure surface. It can be seen that the edge of the opening 903a and the edge of the opening 903b have wide light intensity distribution due to diffraction of light.
FIG. 18D shows an example where a contact hole 910a and a contact hole 910b are formed in an interlayer insulating layer which is formed over a semiconductor layer 906 and a gate electrode 908. When of the openings 903a and 903b are 1.5 μm, sizes of the contact holes 910a and 910b are formed to have a longer size than 1.5 μm due to the influence of the light intensity distribution shown in FIG. 18C. Assuming that the possible misalignment of the photomask is approximately 0.5 μm, a mask pattern has to be designed to include a redundancy of approximately 0.5 μm in order to avoid misalignment of the contact holes 910a and 910b out of the semiconductor layer 906. That is, the conventional lithography process requires an extra margin due to low-resolution lithography, and thus it has limits on the miniaturization of integrated circuits.